3-Dimensional Finite Element Modeling of Integrated Circuit Capacitances

This chapter presents an accurate and efficient method for determination of parasitic capacitances in submicron integrated circuits. The method uses a 3-D finite element model in which the conductor charges are approximated by a piece-wise linear function on a web of edges located on the surface of the conductors. This yields a system of Green’s function integral equations that is solved by a novel approximate matrix inversion technique that only utilizes the entries corresponding to pairs of finite elements that are physically close to each other. With N representing the size of the layout, this results in time and space complexities of O (N) and O (√dd N ) respectively. The method has been implemented in an efficient 3dimensional layout verification program and experimental results are presented.